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ABB PCD232A 3BHE022293R0101 勵(lì)磁控制模塊

     系統(tǒng)的軟件設(shè)計(jì)根據(jù)硬件結(jié)構(gòu)的總體劃分，也可以分為兩大部分來描述。整個(gè)系統(tǒng)的運(yùn)行如圖2所示，F(xiàn)PGA和DSP各自的程序獨(dú)立運(yùn)行，通過中斷信號(hào)完成數(shù)據(jù)的實(shí)時(shí)交互。FPGA向DSP方向的指令是通過FPGA發(fā)送一個(gè)EDMA請(qǐng)求，DSP通過響應(yīng)EDMA請(qǐng)求，建立EDMA通道，開始從FIFO中進(jìn)行預(yù)處理后數(shù)據(jù)的讀取，DSP向FPGA傳輸數(shù)據(jù)時(shí)，通過向FPGA發(fā)送一個(gè)中斷信號(hào)，讓其從FIFO中把壓縮后的圖像數(shù)據(jù)讀出來。

整個(gè)系統(tǒng)工作流程可以簡(jiǎn)單描述如下：系統(tǒng)上電后，首先DSP由flash實(shí)現(xiàn)自舉，并運(yùn)行引導(dǎo)程序，之后轉(zhuǎn)入EDMA等待狀態(tài)，F(xiàn)PGA初始化后等待外部圖像采集命令，收到圖像采集命令后開始進(jìn)行圖像采集，并對(duì)采集到的圖像進(jìn)行預(yù)處理，預(yù)處理后的圖像經(jīng)過FIFO緩沖，在存儲(chǔ)一定量的數(shù)據(jù)之后，F(xiàn)PGA通過半滿信號(hào)向DSP發(fā)送EDMA請(qǐng)求，等待DSP響應(yīng)，DSP一旦收到來自FPGA的EDMA請(qǐng)求，立即建立EDMA通道，從FIFO中讀取數(shù)據(jù)到L2存儲(chǔ)器，存滿一幀圖像后DSP開始圖像壓縮，等待一幅圖像壓縮完成之后，DSP會(huì)向FPGA發(fā)送中斷信號(hào)，F(xiàn)PGA在收到中斷信號(hào)后開始從 FIFO中讀取壓縮后的圖像數(shù)據(jù)。一幀數(shù)據(jù)讀完后，判斷編碼信號(hào)是否有效，如果有效則按同樣的規(guī)則對(duì)下一幀圖像進(jìn)行壓縮，如果無效則通知DSP結(jié)束。

The software design of the system can also be described in two parts based on the overall division of the hardware structure. The entire system runs as shown in Figure 2, with FPGA and DSP programs running independently and completing real-time data exchange through interrupt signals. The instruction from FPGA to DSP is to send an EDMA request through FPGA. DSP responds to the EDMA request, establishes an EDMA channel, and starts reading preprocessed data from FIFO. When DSP transmits data to FPGA, it sends an interrupt signal to FPGA to read the compressed image data from FIFO.

The entire system workflow can be briefly described as follows: After the system is powered on, the DSP is first booted by flash and the boot program is run. Then, it enters the EDMA waiting state. After FPGA initialization, it waits for external image acquisition commands. After receiving the image acquisition commands, it starts image acquisition and preprocesses the collected images. The preprocessed images are buffered in FIFO and stored in a certain amount of data, The FPGA sends an EDMA request to the DSP through a half full signal, waiting for the DSP to respond. Once the DSP receives an EDMA request from the FPGA, it immediately establishes an EDMA channel and reads data from the FIFO into the L2 memory. After one frame of image is filled, the DSP starts image compression. After waiting for an image compression to be completed, the DSP sends an interrupt signal to the FPGA. After receiving the interrupt signal, the FPGA starts reading the compressed image data from the FIFO. After reading a frame of data, determine whether the encoded signal is valid. If it is valid, compress the next frame of image according to the same rules. If it is invalid, notify the DSP to end.

ABB 全系列高壓模塊 伺服控制器：PCD232A 3BHE022293R0101 勵(lì)磁控制模塊

GFD233A 3BHE022294R0103

FET3251C0P184C0H2

5SHY3545L0009

3BHB013085R0001

3BHE009681

5SHX08F4502

CP405 A0 1SAP500405R0001

PM866-2 3BSE050201R1

DI04

CAI04

PM866-23BSE050201R1

PU515A 3BSE032401R1

ICSE08B5 FPR3346501R1012

R474A11XE

REF615A_E

PM864AK01 3BSE018161R1

PCD232A 3BHE022293R01

REF542PLUS 1VCF752000

PPD113B03-26-100100

3BHE023584R2625

PP865A 3BSE042236R2

3ASC25H216A DATX132

3ASC25H208 DATX100

3ASC25H214 DATX130

3ASC25H204 DAPU100

3ASC25H219B DATX133

PPD512A10-150000

LWN2660-6

REF615E E

UNITR0L 1020 UNS0119A-Z,V1

3BHE030579R0003

C1570 3BSE001440R1

PP865A 3BSE042236R2

1MRK00008-KB