文章來自：?https://www.servethehome.com/sifive-p870-risc-v-processor-at-hot-chips-2023/

原標(biāo)題：SiFive P870 RISC-V Processor at Hot Chips 2023

SiFive has been a major RISC-V player for the past few years. At Hot Chips 2023, the company went into the SiFive P870 processor in quite a bit of detail.
SiFive 在過去幾年中一直是 RISC-V 的主要參與者。 在 Hot Chips 2023 上，該公司相當(dāng)詳細地介紹了 SiFive P870 處理器。（編者：偶爾有朋友提到或混淆“Sifive”和“Starfive", 這兩家公司也許當(dāng)初有一段蜜月期，但今天他們基本就是IP vendor(Sifive）和客戶SoC IDH（Starfive，中文名稱:賽昉，中國公司）的關(guān)系了。另外還有一家名為LeapFive（中文名稱：躍昉）的中國公司，這里就不太多八卦了）。

The new RISC-V CPU has standards. That is a big part of the SiFive messaging.

SiFive had its first out-of-order chip in the P550 in 2022. The company now has P650/P670 and the P450/P470. Now, there is the P870 and P870-A. A is for Automotive here.

SiFive 于 2022 年在 P550 中推出了首款亂序芯片。該公司現(xiàn)在擁有 P650/P670 和 P450/P470。 現(xiàn)在，有 P870 和 P870-A。 這里的 A 代表汽車。

（編者：在SOHPGO推出了基于平頭哥的C910V的多核處理器后，將在它的下一代芯片中將考慮采用Sifive的P670。平頭哥的內(nèi)耗正在將一手好牌打的稀爛？）????????

SiFive P870 RISC V HC35_Page_03

SiFive is building larger and more complex chips now. Something that is different is that the solution utilizes a shared L2 cache. Many Arm CPUs today are working on dedicated L2 caches for cloud workloads.

SiFive 現(xiàn)在正在制造更大、更復(fù)雜的芯片。 不同之處在于該解決方案利用共享 L2 緩存。 如今，許多 Arm CPU 都在為云工作負載提供專用的二級緩存。

Here is the pipeline.

Here is the microarchitecture of the chip. This is more of an instruction flow diagram.

Here is the start of the walk-through on this one starting at the top.

Here SiFive is handling fusion functions here and the ROB of 1120 is being noted as an extreme case. This is basically counting bundled instructions from what it sounds like (maybe this is comparable to 280 in other architectures.)?

這里 SiFive 正在處理融合函數(shù)，1120 的 ROB 被認為是一個極端情況。 這聽起來基本上是捆綁指令（也許這與其他架構(gòu)中的 280 條指令相當(dāng)）。

The vector sequencer is being noted as a bit of a unique feature for RISC-V.

Just noting at this point that this is more complex than SiFive’s old solutions.

此時請注意，這比 SiFive 的舊解決方案更復(fù)雜。

Still going with more microarchitecture details that one can read.

Here are the specs on the load/ store.

L2 cache is non-inclusive but not exclusive.

Here is what the cluster topology looks like. L1 with 16-cycle latency to a larger L2. This is designed for data sharing between cores in the cluster. This is a 32-core chip example with 8x 4-core clusters.

這是集群拓撲的樣子。 L1 到更大的 L2 具有 16 個周期的延遲。 這是為集群中的核心之間的數(shù)據(jù)共享而設(shè)計的。 這是一個具有 8 個 4 核集群的 32 核芯片示例。

Here is a consumer topology with two P870 higher-performance cores, four P470’s, smaller more efficient cores in a cluster, and then a low-power E6 in-order core for always-on at low power.

這是一個消費類拓撲，其中有兩個 P870 高性能核心、四個 P470、集群中更小、更高效的核心，然后是一個低功耗 E6 有序核心，可在低功耗下始終開啟。

Here is the new SiFive P870-A automotive safety feature slide. Here more focus is on fault detection, reliability, and safety. The P870-A has things like parity in register files, and the caches have ECC as some examples of how this is different.

這是新型 SiFive P870-A 汽車安全功能幻燈片。 這里更關(guān)注的是故障檢測、可靠性和安全性。 P870-A 在寄存器文件中具有奇偶校驗等功能，并且緩存具有 ECC 功能，這可以作為其不同之處的一些示例。

SiFive has a number of different types of IP. Here is a full list. Before seeing this list, I had no idea they had this variety of IP.

這是SiFive多種不同類型的 IP完整列表。 在看到這個列表之前，我不知道他們有這么多的 IP。

The next generation that we will hear about is the Napa core.

我們將聽到的下一代是 Napa 核心。

Final Words

This is not a product announcement. The product announcement will be in a few weeks apparently and the clock speeds are expected to be in the 3GHz range. This was cool to hear about. RISC-V has a lot of momentum and SiFive has been a big player. SiFive is almost starting to feel like it is trying to become the Arm of the RISC-V market but with RISC-V as an ecosystem being open.

這不是產(chǎn)品公告。 該產(chǎn)品顯然將在幾周內(nèi)發(fā)布，時鐘速度預(yù)計將在 3GHz 范圍內(nèi)。 聽到這個消息真是太酷了。 RISC-V 發(fā)展勢頭強勁，SiFive 一直是其中的重要參與者。 SiFive 幾乎開始讓人感覺它正在試圖成為 RISC-V 市場的手臂，但 RISC-V 作為一個開放的生態(tài)系統(tǒng)。