ABB PFSK152 綜合保護(hù)繼電器
PLC主要應(yīng)用的領(lǐng)域
1．開關(guān)量邏輯控制
取代傳統(tǒng)的繼電器電路，實(shí)現(xiàn)邏輯控制、順序控制，既可用于單臺(tái)設(shè)備的控制，也可用于多機(jī)群控及自動(dòng)化流水線。如注塑機(jī)、印刷機(jī)、訂書機(jī)械、組合機(jī)床、磨床、包裝生產(chǎn)線、電鍍流水線等。
2．工業(yè)過程控制
在工業(yè)生產(chǎn)過程當(dāng)中，存在一些如溫度、壓力、流量、液位和速度等連續(xù)變化的量（即模擬量），PLC采用相應(yīng)的A/D和D/A轉(zhuǎn)換模塊及各種各樣的控制算法程序來處理模擬量，完成閉環(huán)控制。PID調(diào)節(jié)是一般閉環(huán)控制系統(tǒng)中用得較多的一種調(diào)節(jié)方法。過程控制在冶金、化工、熱處理、鍋爐控制等場(chǎng)合有非常廣泛的應(yīng)用。
3．運(yùn)動(dòng)控制
PLC可以用于圓周運(yùn)動(dòng)或直線運(yùn)動(dòng)的控制。一般使用專用的運(yùn)動(dòng)控制模塊，如可驅(qū)動(dòng)步進(jìn)電機(jī)或伺服電機(jī)的單軸或多軸位置控制模塊，廣泛用于各種機(jī)械、機(jī)床、機(jī)器人、電梯等場(chǎng)合。
4．?dāng)?shù)據(jù)處理
PLC具有數(shù)學(xué)運(yùn)算（含矩陣運(yùn)算、函數(shù)運(yùn)算、邏輯運(yùn)算）、數(shù)據(jù)傳送、數(shù)據(jù)轉(zhuǎn)換、排序、查表、位操作等功能，可以完成數(shù)據(jù)的采集、分析及處理。數(shù)據(jù)處理一般用于如造紙、冶金、食品工業(yè)中的一些大型控制系統(tǒng)。
5．通信及聯(lián)網(wǎng)
PLC通信含PLC間的通信及PLC與其它智能設(shè)備間的通信。隨著工廠自動(dòng)化網(wǎng)絡(luò)的發(fā)展，現(xiàn)在的PLC都具有通信接口，通信非常方便。
DSP的性能受其對(duì)存儲(chǔ)器子系統(tǒng)的管理能力的影響。如前所述，MAC和其它一些信號(hào)處理功能是DSP器件信號(hào)處理的基本能力，快速M(fèi)AC執(zhí)行能力要求在每個(gè)指令周期從存儲(chǔ)器讀取一個(gè)指令字和兩個(gè)數(shù)據(jù)字。有多種方法實(shí)現(xiàn)這種讀取。比如，使用多接口存儲(chǔ)器（允許在每個(gè)指令周期內(nèi)對(duì)存儲(chǔ)器多次訪問）、分離指令和數(shù)據(jù)存儲(chǔ)器（“哈佛”結(jié)構(gòu)及其派生類）以及指令緩存（允許從緩存讀取指令而不是存儲(chǔ)器，從而將存儲(chǔ)器空閑出來用作數(shù)據(jù)讀?。?span style="max-width: 100%; text-indent: 2em;">另外要注意所支持的存儲(chǔ)器空間的大小。許多定點(diǎn)DSP的主要目標(biāo)市場(chǎng)是嵌入式應(yīng)用系統(tǒng)，在這種應(yīng)用中存儲(chǔ)器一般較小，所以這種DSP器件具有小到中等片上存儲(chǔ)器（4K到64K字左右），備有窄的外部數(shù)據(jù)總線。另外，絕大多數(shù)定點(diǎn)DSP的地址總線小于或等于16位，因而可外接的存儲(chǔ)器空間受到限制一些浮點(diǎn)DSP的片上存儲(chǔ)器很小，甚至沒有，但外部數(shù)據(jù)總線寬。例如TI公司的TMS320C30只有6K片上存儲(chǔ)器，外部總線為24位，13位外部地址總線。而ADI的ADSP2-21060具有4Mb的片上存儲(chǔ)器，可以多種方式劃分為程序存儲(chǔ)器和數(shù)據(jù)存儲(chǔ)器。選擇DSP時(shí)，需要根據(jù)具體應(yīng)用對(duì)存儲(chǔ)空間大小以及對(duì)外部總線的要求來選擇。
DSP processors and devices such as Intel, Pentium, or powerGeneral purpose processors (GPPS) of PC have great differences. These differences arise from the fact that the structure and instructions of DSPs are specially designed and developed for signal processing. It has the following characteristics.In order to effectively complete multiplication and accumulation operations such as signal filtering, the processor must perform effective multiplication operations. GPPS was not originally designed for heavy multiplication operations. The first major technical improvement that distinguishes DSPs from early GPPS is the addition of specialized hardware and explicit MAC instructions that can perform single cycle multiplication operations.Traditional GPPS use von Neumann storage structure, in which a storage space is connected to the processor core through two buses (an address bus and a data bus). This structure cannot meet the requirement that MAC must access the memory four times in an instruction cycle. DSPs generally use Harvard structure, in which there are two storage spaces: program storage space and data storage space. The processor core is connected to these storage spaces through two sets of buses, allowing two simultaneous accesses to the memory. This arrangement doubles the bandwidth of the processor. In Harvard architecture, sometimes a larger storage bandwidth is achieved by adding a second data storage space and bus. Modern high-performance GPPS usually have two on-chip cache memories, one for storing data and one for storing instructions. Theoretically, this dual on-chip cache and bus connection is equivalent to the Harvard structure. However, GPPS use control logic to determine which data and instruction words reside in the on-chip cache, which is usually not seen by the programmer. In DSPs, the programmer can clearly control which data and instructions are stored in the on-chip storage unit or cache.
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